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DATASHEET
SPREAD SPECTRUM CLOCK GENERATOR Description
The IDT5V50009 generates a low EMI output clock and a reference clock from a clock or crystal input. The part is designed to lower EMI through the application of spreading a clock. Using IDT's proprietary mix of analog and digital Phase-Locked Loop (PLL) technology, the device spreads the frequency spectrum of the output, reducing the frequency amplitude peaks by several dB depending on spread range. The IDT5V50009 offers a range of down spread from a high speed clock or crystal input. The IDT5V50009 generates one modulated (SSCLK) and unmodulated (REFCLK) clock. The modulated clock is controlled by the select pin, and the unmodulated clock has the same frequency as the input clock or crystal.
IDT5V50009
Features
* * * * * * * *
Packaged in 8-pin SOIC Available in Pb (lead) free package Input frequency range 20- 40 MHz Provides modulated and unmodulated clocks Accepts a clock or crystal input Provides down spread modulation Provides power down function Reduce electromagnetic interference (EMI) by 8-16 db
* Operating voltage of 3.3 V * Advanced, low-power CMOS process
Block Diagram
VDD
PD S0 PLL Clock Synthesis and Spread Spectrum Circuitry REFCLK
X1/CLK Clock Buffer/ Crystal Ocsillator X2 External caps required for with crystal for accurate tuning of the clock
SSCLK
GND
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Pin Assignment
X1/ICLK GND S0 SSCLK 1 2 3 4 8 7 6 5 X2 VDD PD REFCLK
Spread Percentage Select Table
S0 0 1 Spread Direction Down Down Spread Percentage (%) -1.25 -1.75
0 = connect to GND
8 p i n ( 1 5 0 mi l ) S O I C
1 = connect directly to VDD * Default has internal pull up resistor to VDD
Pin Descriptions
Pin Number
Pin Name
Pin Type
Pin Description
1 2 3 4 5 6 7 8
X1/ICLK GND S0 SSCLK REFCLK PD VDD X2
Input Power Input Output Output Input Power Input
Connect to a 20 to 40 MHz crystal or clock. Connect to ground. Select spread percentage per table above. Weak Internal pull-up. Spread spectrum clock output per table above. Weak Internal Pull down CMOS level clock output matches the nominal frequency of the input crystal or clock. Weak Internal Pull down Power down tri-state. This pin powers down entire chip and tri-state the outputs when low. Weak Internal pull-up. Connect to 3.3 V. Connect to a 20 to 40 MHz crystal or leave unconnected.
IDTTM SPREAD SPECTRUM CLOCK GENERATOR
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External Components
The IDT5V50009 requires a minimum number of external components for proper operation.
Crystal Information
The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 In the equation, CL is the crystal load capacitance. So, for a crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected between VDD and GND, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 .
Spread Spectrum Profile
The IDT5V50009 low EMI clock generator uses an optimized frequency slew rate algorithm to facilitate down stream tracking of zero delay buffers and other PLL devices. The frequency modulation amplitude is constant with variations of the input frequency.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the IDT5V50009. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Modulation R ate
Frequency
Time
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V50009. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70 C -65 to +150 C 125 C 260 C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +2.97
Typ.
Max.
+70 3.63
Units
C V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V +10%, Ambient Temperature 0 to +70 C
Parameter
Power Supply Range Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Power Supply Current. Operating Power Supply Current Stand by Input Capacitance Clock Output Impedance Internal Pull-up Resistor Internal Pull-down Resistor
Symbol
VDD VIH VIL VOH VOL IDD IDD CIN RPU RPd
Conditions
S0 Input S0 Input IOH =-12 ma, SSCLK and REFCLK IOL =12ma, SSCLK FIN =32 MHz, no load PD = GND
Min.
2.97 2.0 0.0 2.4
Typ.
3.3 0.0
Max.
3.63 0.8
Units
V V V V
0.4 19.0 150 5 20 23.0 250
V mA A pF ohms k k
So, PD SSCLK
550 240
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V +10%, Ambient Temperature 0 to +70 C
Parameter
Input Clock Frequency Output Clock Frequency Clock Rise Time Clock Fall Time Output Clock Duty Cycle Cycle-to-Cycle Jitter
Symbol
Conditions
Min.
20 20
Typ.
Max. Units
40 40 MHz MHz ns ns 55 350 % ps
trise1 tfall1
SSCLK and REFCLK, 0.8 V to 2.0 V SSCLK and REFCLK, 0.8 V to 2.0 V SSCLK and REFCLK @1.65V SSCLK, Fin=27MHz, Fout=27MHz REFCLK, Fin=27MHz, Fout=27MHz Input/512 39 45
0.75 0.75 50 250
Cycle-to-Cycle Jitter
275
375
ps
Modulation rate EMI Peak Frequency Reduction
78 8 to 16
kHz dB
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
110 100 80 35
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
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Marking Diagram (Pb free)
8 5
IDT5V50 009DCG ZYYWW$
1
Notes: 1. "Z" is the device step (1 to 2 characters). 2. YYWW is the last two digits of the year and week that the part was assembled. 3. "$" is the assembly mark code. 4. "G" after the two-letter package code designates RoHS compliant package. 5. Bottom marking: country of origin if not USA.
4
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Package Outline and Package Dimensions (8 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Min Max Inches Min Max
Symbol
Index Area
EH
Pin 1
D
h x 45 0
A A1 B C D E e H h L a
1.35 1.75 1.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 Basic 5.80 6.20 0.25 0.50 0.40 1.27 0 8
0.0532 0.0688 0.0040 0.0098 0.013 0.020 0.0075 0.0098 .1890 .1968 0.1497 0.1574 0.050 Basic 0.2284 0.2440 0.010 0.020 0.016 0.050 0 8
A Q e b c
Ordering Information
Part / Order Number
5V50009DCG 5V50009DCG8
Marking
See page 6
Shipping Packaging
Tubes Tape and Reel
Package
8-pin SOIC 8-pin SOIC
Temperature
0 to +70 C 0 to +70 C
Parts that are ordered with a "G" after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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www.IDT.com
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800-345-7015 408-284-8200 Fax: 408-284-2775
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www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc. www.idt.com
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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